Cadence Expands System IP Portfolio with NoC for Optimized Electronic System Connectivity
七月 8 2025
2025-07
Passive Components
Caddock Electronics
Cadence Electronics (USA) recently announced the expansion of its system IP portfolio with the addition of Cadence® Janus™ Network-on-Chip (NoC). As today's computing needs continue to increase, larger and more complex system-on-chips (SoCs) and disaggregated multi-chip systems are rapidly gaining popularity in the market, and data transmission within and between silicon components has become increasingly challenging, affecting power, performance and area (PPA). Cadence Janus NoC can efficiently manage these synchronous high-speed communications with extremely low latency, helping customers achieve their PPA goals faster with lower risk.
"Cadence is a trusted leader in IP and design quality, and we continue to invest in our foundational interface and processor IP, system IP, software and design services to help customers develop differentiated disaggregated designs," said Boyd Phelps, senior vice president and general manager of the Silicon Solutions Group at Cadence. "The addition of the Cadence Janus NoC to our growing IP portfolio system is an important milestone in this strategy. We are moving from an IP provider to a SoC design partner, bringing greater value to our customers, allowing them to focus their valuable engineering resources on differentiating their silicon."
The Cadence Janus NoC is based on Cadence’s trusted and proven Tensilica® RTL generation tools. Customers can use Cadence’s broad portfolio of hardware and software products to perform software and hardware simulation of their NoCs, and use Cadence’s System Performance Analysis (SPA) tool to gain insight into the performance of the NoC. The flow supports architectural exploration to help achieve the best NoC design to meet product requirements. The NoC is built on Cadence’s long-standing leadership in IP and design quality, supported by a team of engineers that leads the way in customer satisfaction.
The Cadence Janus NoC effectively addresses the routing congestion and timing issues associated with today’s complex SoC interconnects that are often not apparent until physical implementation. Cadence’s first-generation NoC not only addresses today’s most pressing needs, but also provides a platform for future innovations, such as support for industry-standard memory and I/O coherency protocols. Features and benefits available today include:
Ease of use: Cadence’s powerful, well-designed graphical user interface (GUI) makes it easy to configure the NoC from small subsystems to full SoCs and future multi-chip systems.
Faster time to market: RTL is optimized for PPA, enabling SoC designers to achieve bandwidth and latency goals. Packetized information improves wire utilization, reduces wire count, and eases timing closure.
Reduced risk: The NoC’s built-in power management, clock domain crossing, and width matching capabilities help reduce design complexity.
Fast design turnaround: Cadence's extensive software simulation and hardware emulation capabilities enable early architectural exploration to quickly validate PPA results and ensure that the configuration meets the design requirements.
Scalable architecture: Customers can design a subsystem and reuse it in the context of a full SoC with a NoC for future reuse in multi-chip systems.
Flexible: Cadence NoCs are compatible with any IP with industry-standard interfaces, including AXI4 and AHB.
"We are excited to see Cadence expand their IP portfolio by investing in system-level solutions," said Suk Lee, vice president and general manager of the Ecosystem Technology Office at Intel Foundry. "NoCs are critical to nearly every subsystem in today's SoCs, so we are very supportive of Cadence's NoC offerings and look forward to their continued expansion of their IP portfolio in the future."
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